1. Field of the Invention
The present invention relates to a semiconductor memory device such as a mask ROM.
2. Prior Art
A conventional semiconductor memory device such as a mask ROM utilizes, as a method for reducing current consumption, a replica circuit having a dummy sense amplifier circuit and a dummy memory cell circuit, which are configured similarly to a normal sense amplifier circuit and a normal memory cell circuit, in order to control an appropriate read operation time. Hereinafter, an operation method for a replica circuit in a conventional mask ROM will be described with reference to the drawings.
FIG. 8 is a diagram showing a read circuit of a conventional mask ROM. A sense amplifier circuit 1 includes: a p-type transistor 2 whose gate input receives a pre-charge signal NPR; an n-type transistor 3 coupled in series to the p-type transistor 2; an inverter 4 whose input is coupled to a source node SA of the n-type transistor 3 and whose output is coupled to a gate input of the n-type transistor 3; an inverter chain 5, an input of which is coupled to the source node SA, and from which an output SOUT0 is outputted; and a charge circuit 6, to which the pre-charge signal NPR is inputted, and an output of which is coupled to the source node SA.
The charge circuit 6 includes a p-type transistor 6(1) and an n-type transistor 6(2). A column gate 7 includes: an n number of n-type transistors 8(1) through 8(n), gate inputs of which receive column selection signals CL1 through CLn, and which are connected between the source node SA and bit lines BL1 through BLn.
A memory cell array 9 includes memory cells 10(1,1) through 10(n, m) arranged in an array, which have gate inputs coupled to word lines WL1 through WLm, and sources each coupled to a ground potential. Whether drains of these memory cells are coupled to the bit lines or not is decided during manufacturing process depending upon data to be stored. In this conventional device, the drains of all the memory cells are coupled to the bit lines. A Y address signal ADY is inputted to a column selection circuit 16, from which column selection signals CL1 through CLn are outputted. An X address signal ADX is inputted to a row selection circuit 17, outputs of which are coupled to the word lines WL1 through WLm.
In a timing generation circuit 21, a dummy sense amplifier circuit 11 is configured similarly to the sense amplifier circuit 1. A dummy column gate 12 includes a transistor 13(1), a gate input of which is coupled to a power supply, and which is configured similarly to those in the column gate 7. A dummy memory cell array 14 includes dummy memory cells 15(1) through 15(m), gate inputs of which are each coupled to a ground potential, which are coupled to a dummy bit line DBL1, and which are configured similarly to the memory cells 10. An external clock signal CLK and an output from an inverter 20 are inputted to an NAND gate 18, from which the pre-charge signal NPR is outputted. An output SOUTD from the dummy sense amplifier circuit 11 is inputted to the inverter 20. The clock signal CLK is inputted to an inverter 19, from which a pre-charge signal NDPR is outputted to the dummy sense amplifier circuit 11.
Next, an operation of the read circuit shown in FIG. 8 will be described with reference to a timing chart shown in FIG. 9. When the external clock signal CLK has been changed from “L” level to “H” level at a time point t0, the level of the pre-charge signal NPR sent from the NAND gate 18 becomes “L” level. Thus, the p-type transistor 2 is turned ON, and the p-type transistor 6(1) of the charge circuit 6 is also turned ON, and therefore, the source node SA is charged. However, drains of memory cells selected by column selection signals CL1 through CLn selected by a column selection circuit 16 and selected via word lines WL1 through WLm selected by a row selection circuit 17 are coupled to the associated bit lines; therefore, the level of the source node SA will not be charged until the determination level of the inverter chain 5 (i.e., sense amplifier determination level), and thus the output SOUT0 with “L” level is outputted. In such a case, during a time period when the pre-charge signal NPR is at “L” level, a through current is kept flowing through the memory cells 10.
Similarly, when the external clock signal CLK has been changed from “L” level to “H” level at the time point t0, the level of the pre-charge signal NDPR sent from the inverter 19 becomes “L” level, and the dummy source node DSA is charged. All the dummy memory cells 15(1) through 15(m) are coupled to the dummy bit line DBL1, and all the dummy word lines are each fixed to a ground potential; therefore, the level of the dummy source node DSA will be charged until the determination level of the inverter chain (i.e., sense amplifier determination level), and thus the output SOUTD with “H” level is outputted. Since the output SOUTD is inputted to the NAND gate 18 via the inverter 20, the level of the pre-charge signal NPR is changed to “H” level to turn the p-type transistor 2 OFF, thus stopping the through current. As a result, the potential of the source node is decreased. Accordingly, the output SOUT is kept at “L” level.
At a time point t100, when the external clock signal CLK has been changed from “H” level to “L” Level, the level of the pre-charge signal NDPR is changed to “H” level, and the potential of the dummy source node DSA is decreased.
As described above, since there is provided the replica circuit that utilizes the dummy memory cells and dummy sense amplifier configured similarly to the normal memory cells and sense amplifier circuit, an appropriate timing can be obtained during the sense amplifier operation time period (see, for example, Japanese Unexamined Patent Publication NO. 08-036895).
However, in recent years, transistor off leak current has been significantly increased due to miniaturization in manufacturing technologies, and therefore, the conventional replica circuit presents a first problem as follows. Since the conventional replica circuit utilizes the dummy bit line to which all the dummy memory cells are coupled, a current supplied from the charge circuit to the dummy bit line becomes insufficient, and thus it becomes impossible to charge the dummy bit line to a predetermined potential and to ensure a desired timing margin. Furthermore, the conventional replica circuit presents a second problem as follows. Due to memory cell off leak current, the charging of the bit line is delayed to cause an access delay, or data output of the sense amplifier becomes later than the timing generated by the replica circuit to cause an erroneous reading.